Challenges and Strategic Drivers in 3D IC Failure Analysis: Closing the Critical Gaps using Designs for Analysis

Engineering notes

Key topics: autonomous driving, control. See the paper for implementation details and experimental results.

Chinese explanation / 中文解读

中文解读待补充：本站会优先为端到端自动驾驶、BEV感知、3D目标检测、轨迹预测、路径规划、LiDAR感知等高价值论文补充中文说明。

Original abstract

Abstract The relentless pursuit of high-performance computing driven by 5G/6G, artificial intelligence, autonomous driving, Internet of things (IoT), quantum computing, and data centers has pushed traditional integrated circuit scaling to its limits [1]. As lithography challenges and escalating manufacturing costs slow Moore’s law, the industry has pivoted toward design technology co-optimization (DTCO) and system technology co-optimization (STCO). These methodologies extend device performance through process and package scaling, introducing complex transistor architectures like gate-all-around (GAA), forksheets, and complementary FETs (CFET), alongside system-level innovations like backside power deliver networks (BPDN), 3D IC, and heterogeneous integration. While these advancements optimize power, performance, area, and cost (PPAC), they inadvertently create a significant bottleneck in failure analysis (FA). Advanced package technologies such as co-packaged optics, heterogeneous integration, and chiplets have fundamentally disrupted electrical fault isolation (EFI) flows. Complex package routing and dense 3D stacking of multiple components now pose severe challenges to fault isolation. Historically, the industry relied on design for test (DFT) to screen defects and design for diagnosis (DFD) to predict failure locations. However, in advanced nodes, diagnostic quality is often insufficient to characterize underlying failure mechanisms, and design complexity restricts accessibility and controllability of internal signals needed for EFI. This paper reviews the impact of DTCO and STCO on failure analysis, identifying key challenges and drivers. FA has traditionally been treated as a post-silicon afterthought; chip and hardware designs rarely consider its workflows. Yet, as new technologies evolve, FA becomes a critical bottleneck to yield learning, slowing down yield ramp-up and time-to-market. This paper calls for a strategic “left-shift” of FA requirements early into the design cycle through design for analysis (DFA). By integrating dedicated DFA features, manufacturers can bridge the gap between silicon design and post-silicon debug, transforming FA into a proactive driver of yield.

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