Autonomous driving paper index
A Retinomorphic Graphene Transistor Implementing Direction‐ and Velocity‐Selective Computation for In‐Sensor Image Stabilization
One-line summary
Neural circuits in the retina extract motion direction and velocity through asymmetric dendritic processing, but replicating these computations in solid-state hardware has not been achieved.
Engineering notes
By suppressing ego-motion-induced global scene jitter within a defined frequency band, the device achieves on-sensor image stabilization with lower latency and power consumption than digital post-processing.
Chinese explanation / 中文解读
中文解读待补充：本站会优先为端到端自动驾驶、BEV感知、3D目标检测、轨迹预测、路径规划、LiDAR感知等高价值论文补充中文说明。
Original abstract
Neural circuits in the retina extract motion direction and velocity through asymmetric dendritic processing, but replicating these computations in solid-state hardware has not been achieved. Herein, a single multi-gate ion-gel graphene transistor (MIG-GFET) is demonstrated to emulate key operations of the direction-selective ganglion cell (DSGC) and starburst amacrine cell (SAC) microcircuit. Spatially distributed gates created artificial dendritic compartments whose ionic dynamics enabled nonlinear summation of sequential inputs, yielding intrinsic direction selectivity without algorithmic post-processing. An oppositely biased inhibitory gate reproduced SAC-like null-side inhibition and yielded a band-pass velocity response with a tunable preferred speed-closely mirroring the spatiotemporal filtering properties underlying direction- and speed-dependent firing in biological DSGCs. This velocity selectivity enables the MIG-GFET to function as an analog motion filter. By suppressing ego-motion-induced global scene jitter within a defined frequency band, the device achieves on-sensor image stabilization with lower latency and power consumption than digital post-processing. Therefore, dendritic-level computation can be embedded directly into a graphene transistor, offering a path toward vision hardware where sensing and early neural processing are co-localized at the device level. This compact, low-power approach is compatible with focal-plane array integration and broad applications in real-time motion analysis.
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