A hierarchical dynamic fault tree and Markov chain framework for safety-critical register localization in automotive-grade SoCs

Engineering notes

Key topics: autonomous driving. See the paper for implementation details and experimental results.

Chinese explanation / 中文解读

中文解读待补充：本站会优先为端到端自动驾驶、BEV感知、3D目标检测、轨迹预测、路径规划、LiDAR感知等高价值论文补充中文说明。

Original abstract

With the rapid development of autonomous driving and intelligent cockpit technologies, the reliability of automotive-grade chips has become the core element in ensuring driving safety. Dynamic fault tree analysis possesses the capability to describe the complex temporal competition dependencies among registers in automotive-grade chips and can satisfy the stringent evaluation requirements for hardware random failures stipulated by the ISO 26262 functional safety standard. However, due to the prevalent issues of state space explosion and low solving efficiency for mixed static/dynamic logic within dynamic fault trees, this paper proposes a hierarchical parsing optimization method. First, this paper proposes a fault hierarchical processing approach that decomposes the dynamic fault tree into two parts—a static main body and dynamic sub-trees—which are solved separately. This process simplifies the complexity of the analysis, the complexity of the fault trees is reduced by an average of 61.5%, fully demonstrating the significant efficacy of this method in fault tree decomposition and simplification. Second, this paper proposes a Markov chain-based dynamic logic gate parsing method that converts the internal dynamic logic relationships of the fault tree into isomorphic state space models. Through this solving process, the system’s failure probability distribution can be obtained, thereby providing a precise mathematical basis for the subsequent quantitative evaluation of register importance in automotive-grade chips.

Links and sources

Comments